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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM67A618A/D
64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM
The MCM67A618A is a 1,179,648 bit latched address static random access memory organized as 65,536 words of 18 bits. The device integrates a 64K x 18 SRAM core with advanced peripheral circuitry consisting of address and data input latches, active low chip enable, separate upper and lower byte write strobes, and a fast output enable. This device has increased output drive capability supported by multiple power pins. Address, data in, and chip enable latches are provided. When latch enables (AL for address and chip enables and DL for data in) are high, the address, data in, and chip enable latches are in the transparent state. If latch enables are tied high the device can be used as an asynchronous SRAM. When latch enables are low the address, data in, and chip enable latches are in the latched state. This input latch simplifies read and write cycles by guaranteeing address and data-in hold time in a simple fashion. Dual write enables (LW and UW) are provided to allow individually DQ9 writeable bytes. LW controls DQ0 - DQ8 (the lower bits) while UW DQ10 controls DQ9 - DQ17 (the upper bits). VCC Six pair of power and ground pins have been utilized and placed on VSS the package for maximum performance. DQ11 The MCM67A618A will be available in a 52-pin plastic leaded chip DQ12 carrier (PLCC). DQ13 This device is ideally suited for systems that require wide data bus DQ14 widths, cache memory, and tag RAMs. VSS * * * * * * * * * Single 5 V 5% Power Supply Fast Access Times: 10/12/15 ns Max Byte Writeable via Dual Write Enables Separate Data Input Latch for Simplified Write Cycles Address and Chip Enable Input Latches Common Data Inputs and Data Outputs Output Enable Controlled Three-State Outputs 3.3 V I/O Compatible High Board Density 52-Lead PLCC Package
VCC DQ15 DQ16 DQ17
MCM67A618A
FN PACKAGE PLASTIC CASE 778-02
PIN ASSIGNMENT
A6 A7 E UW LW VCC V SS DL AL G A8 A9 A10 7 6 5 4 3 2 1 52 51 50 49 48 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DQ8 DQ7 DQ6 VCC VSS DQ5 DQ4 DQ3 DQ2 VSS VCC DQ1 DQ0 All power supply and ground pins must be connected for proper operation of the device. A5 A4 A3 A2 A1 A0 V SS V CC A15 A14 A13 A12 A11
PIN NAMES
A0 - A15 . . . . . . . . . . . . . . . . Address Inputs AL . . . . . . . . . . . . . . . . . . . . . . Address Latch DL . . . . . . . . . . . . . . . . . . . . . . . . . Data Latch LW . . . . . . . . . . . . Lower Byte Write Enable UW . . . . . . . . . . . . Higher Byte Write Enable E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ0 - DQ17 . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 1 10/9/96
(c) Motorola, Inc. 1996 MOTOROLA FAST SRAM
MCM67A618A 1
BLOCK DIAGRAM
A0 - A15 16 LATCH 16 MEMORY ARRAY 64K x 18 18
OUTPUT BUFFER
DQ0 - DQ17 18
18 9 9 WRITE AMP E LATCH CONTROL 18 LATCH
AL LW UW G DL
TRUTH TABLE
E H L L L L L L L LW X X X H H L L L UW X X X H H L L H AL* X L H X X X X X DL* X X X X X L H X G X X X L H X X X Mode Deselected Cycle Read or Write Using Latched Addresses Read or Write Using Unlatched Addresses Read Cycle Read Cycle Write Both Bytes Using Latched Data In Write Both Bytes Using Unlatched Data In Write Cycle, Lower Byte Supply Current ISB ICC ICC ICC ICC ICC ICC ICC I/O Status High-Z -- -- Data Out High-Z High-Z High-Z High-Z
L H L X X X Write Cycle, Lower Byte ICC High-Z *E and Addresses satisfy the specified setup and hold times for the falling edge of AL. Data-in satisfies the specified setup *and hold times for falling edge of DL. NOTE: This truth table shows the application of each function. Combinations of these functions are valid.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to 7.0 - 0.5 to VCC + 0.5 30 1.6 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MCM67A618A 2
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.75 2.2 - 0.5* Max 5.25 VCC + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) for I 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 20 ns) for I 20.0 mA.
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (G = VIH) AC Standby Current (G = VIH, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tAVAV min) AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tAVAV min) CMOS Standby Current (E VCC - 0.2, All Inputs VCC - 0.2 V or 0.2 V, f = fmax) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) ICCA10 ICCA12 ICCA15 ISB1 ISB2 VOL VOH Min -- -- -- Max 1.0 1.0 290 280 265 95 20 0.4 3.3 Unit A A mA
-- -- -- 2.4
mA mA V V
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance (All Pins Except DQ0 - DQ17) Input/Output Capacitance (DQ0 - DQ17) Symbol Cin CI/O Typ 4 6 Max 5 8 Unit pF pF
MOTOROLA FAST SRAM
MCM67A618A 3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . Figure 1a Unless Otherwise Noted
ASYNCHRONOUS READ CYCLE TIMING (See Notes 1 and 2)
MCM67A618A-10 MCM67A618A-12 MCM67A618A-15 Parameter Read Cycle Times Access Times: Address Valid to Output Valid E Low to Output Valid Output Enable Low to Output Valid Output Hold from Address Change Output Buffer Control: E Low to Output Active G Low to Output Active E High to Output High-Z G High to Output High-Z tAVQV tELQV tGLQV tAXQX tELQX tGLQX tEHQZ tGHQZ -- -- -- 4 3 1 2 2 10 10 5 -- -- -- 5 5 -- -- -- 4 3 1 2 2 12 12 6 -- -- -- 6 6 -- -- -- 4 3 1 2 2 15 15 7 -- -- -- 7 7 ns ns 5 Symbol tAVAV Min 10 Max -- Min 12 Max -- Min 15 Max -- Unit ns ns Notes 3 4
Power Up Time tELICCA 0 -- 0 -- 0 -- ns NOTES: 1. AL and DL are equal to VIH for all asynchronous cycles. 2. Both Write Enable signals (LW, UW) are equal to VIH for all read cycles. 3. All read cycle timing is referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. Transition is measured 500 mV from steady-state voltage with output load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, tEHQZ is less than tELQX and tGHQZ is less than tGLQX for a given device.
+5V 480 OUTPUT Z0 = 50 RL = 50 VL = 1.5 V OUTPUT 255 5 pF
(a) Figure 1. AC Test Loads
(b)
MCM67A618A 4
MOTOROLA FAST SRAM
ASYNCHRONOUS READ CYCLES
AL (ADDRESS LATCH)
A (ADDRESS)
A1 tAVAV
A2
A3
E (CHIP ENABLE) tELQV tELQX Q (DATA OUT) tAVQV tAXQX Q(A1) tGHQZ Q(A2) tGLQX tGLQV G (OUTPUT ENABLE) LW, UW (WRITE ENABLE) DL (DATA LATCH) tEHQZ Q(A3)
MOTOROLA FAST SRAM
MCM67A618A 5
ASYNCHRONOUS WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM67A618A-10 MCM67A618A-12 MCM67A618A-15 Parameter Write Cycle Times Setup Times: Address Valid to End of Write Address Valid to E High Address Valid to W Low Address Valid to E Low DataValid to W High Data Valid E High W High to Address Invalid E High to Address Invalid W High to Data Invalid E High to Data Invalid Symbol tAVAV tAVWH tAVEH tAVWL tAVEL tDVWH tDVEH tWHAX tEHAX tWHDX tEHDX tWLWH tWLWH tWLEH tELWH tELEH tWHQX tWLQZ Min 10 9 9 0 0 5 5 0 0 0 0 9 8 9 9 9 3 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 Min 12 10 10 0 0 6 6 0 0 0 0 10 9 10 10 10 3 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6 Min 15 13 13 0 0 7 7 0 0 0 0 13 12 13 13 13 3 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 Unit ns ns Notes 4
Hold Times:
ns
Write Pulse Width: Write Pulse Width (G Low) Write Pulse Width (G High) Write Pulse Width Enable to End of Write Enable to End of Write Output Buffer Control: W High to Output Active W Low to Output High-Z
ns 5 6 5, 6 ns 7 7, 8
NOTES: 1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW. 2. AL and DL are equal to VIH for all asynchronous cycles. 3. Both Write Enables must be equal to VIH for all address transitions. 4. All write cycle timing is referenced from the last valid address to the first transitioning address. 5. If E goes high coincident with or before W goes high the output will remain in a high impedance state. 6. If E goes low coincident with or after W goes low the output will remain in a high impedance state. 7. Transition is measured 500 mV from steady-state voltage with output load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, tWLQZ is less than tWHQX for a given device. 8. If G goes low coincident with or after W goes low the output will remain in a high impedance state.
MCM67A618A 6
MOTOROLA FAST SRAM
ASYNCHRONOUS WRITE CYCLE
AL (ADDRESS LATCH)
A (ADDRESS)
A1 tAVAV
A2 tAVWH
A3 tEHAX
A4 tAVEH tAVEL tELEH
E (CHIP ENABLE) tELWH tWHAX LW, UW (WRITE ENABLE) tWHDX tDVWH DATA-IN D(A1) D(A2) tDVEH D(A3) tAVWL tWLWH tWLEH
tEHDX
D(A4)
DL (DATA LATCH) tWHQX Q (DATA OUT) tWLQZ
G (OUTPUT ENABLE)
MOTOROLA FAST SRAM
MCM67A618A 7
LATCHED READ CYCLE TIMING (See Notes 1 and 2)
MCM67A618A-10 MCM67A618A-12 MCM67A618A-15 Parameter Read Cycle Times Access Times: Address Valid to Output Valid E Low to Output Valid AL High to Output Valid Output Enable Low to Output Valid Setup Times: Address Valid to AL Low E Valid to AL Low Address Valid to AL High E Valid to AL High Hold Times: AL Low to Address Invalid AL Low to E Invalid Output Hold: Address Invalid to Output Invalid AL High to Output Invalid Address Latch Pulse Width Output Buffer Control: E Low to Output Active G Low to Output Active AL High to Output Active E High to Output High-Z AL High to Output High-Z G High to Output High-Z tALLAX tALLEX tAXQX tALHQX1 tALHALL tELQX tGLQX tALHQX2 tEHQZ tALHQZ tGHQZ 2 2 4 4 5 3 1 3 2 2 2 -- -- -- -- -- -- -- -- 5 5 5 2 2 4 4 5 3 1 3 2 2 2 -- -- -- -- -- -- -- -- 6 6 6 3 3 4 4 5 3 1 3 2 2 2 -- -- ns -- -- -- -- -- -- 9 9 7 ns ns 5 tAVALL tEVALL tAVALH tEVALH 2 2 0 0 -- -- -- -- 2 2 0 0 -- -- -- -- 2 2 0 0 -- -- -- -- ns tAVQV tELQV tALHQV tGLQV -- -- -- -- 10 10 10 5 -- -- -- -- 12 12 12 6 -- -- -- -- 15 15 15 7 ns 4 4 Symbol tAVAV Min 10 Max -- Min 12 Max -- Min 15 Max -- Unit ns ns 3 4 Notes 3
4
NOTES: 1. Both Write Enable Signals (LW, UW) are equal to VIH for all read cycles. 2. All read cycle timing is referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. All latched inputs must meet the specified setup and hold times with stable logic levels for ALL falling edges of address latch (AL) and data latch (DL). 5. Transition is measured 500 mV from steady-state voltage with output load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, tEHQZ is less than tELQX and tALHQZ is less than tALHQX2 and tGHQZ is less than tGLQX for a given device.
MCM67A618A 8
MOTOROLA FAST SRAM
LATCHED READ CYCLES
AL (ADDRESS LATCH) tALLAX tAVALL A (ADDRESS) A1 tALLEX tEVALL E (CHIP ENABLE) tEHQZ Q (DATA OUT) tALHQX2 tGLQX G (OUTPUT ENABLE) LW, UW (WRITE ENABLE) DL (DATA LATCH) tGLQV tELQV tELQX tALHQX1 Q(A1) Q(A2) tALHQV tAVQV tAXQX Q(A2) tALHQZ tEVALH tAVALH tALHALL
A2 tAVAV
A3
Q(A3)
tGHQZ
MOTOROLA FAST SRAM
MCM67A618A 9
LATCHED WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM67A618A-10 MCM67A618A-12 MCM67A618A-15 Parameter Write Cycle Times: Address Valid to Address Valid Setup Times: Address Valid to End of Write Address Valid to End of Write E Valid to AL Low Address Valid to AL Low E Valid to AL High Address Valid to AL High AL High to W Low Address Valid to W Low Address Valid to E Low Data Valid to DL Low Data Valid to W High Data Valid to E High DL High to W High DL High to E High Hold Times: AL Low to E High AL Low to Address Invalid DL Low to Data Invalid W High to Address Invalid E High to Address Invalid W High to Data Invalid E High to Data Invalid W High to DL High E High to DL High W High to AL High Write Pulse Width: AL High to W High Write Pulse Width (G Low) Write Pulse Width (G High) Write Pulse Width Enable to End of Write Enable to End of Write Address Latch Pulse Width Output Buffer Control: W High to Output Active W Low to Output High-Z tALHWH tWLWH tWLWH tWLEH tELWH tELEH tALHALL tWHQX tWLQZ 9 9 8 9 9 9 5 3 -- -- -- -- -- -- -- -- -- 5 10 10 9 10 10 10 5 3 -- -- -- -- -- -- -- -- -- 6 13 13 12 13 13 13 5 3 -- -- -- -- -- -- -- -- -- 9 ns ns 8 8, 9 tALLEH tALLAX tDLLDX tWHAX tEHAX tWHDX tEHDX tWHDLH tEHDLH tWHALH 2 2 2 0 0 0 0 0 0 0 -- -- -- -- -- -- -- -- -- -- 2 2 2 0 0 0 0 0 0 0 -- -- -- -- -- -- -- -- -- -- 3 3 3 0 0 0 0 0 0 0 -- -- -- -- -- -- -- -- -- -- ns 5 tAVWH tAVEH tEVALL tAVALL tEVALH tAVALH tALHWL tAVWL tAVEL tDVDLL tDVWH tDVEH tDLHWH tDLHEH 9 9 2 2 0 0 0 0 0 2 5 5 5 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 10 2 2 0 0 0 0 0 2 6 6 6 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 13 13 2 2 0 0 0 0 0 2 7 7 7 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns 4 4 Symbol tAVAV Min 10 Max -- Min 12 Max -- Min 15 Max -- Unit ns ns Notes 4
6 7 6, 7 4
NOTES: 1. W (write) refers to either one or both byte write enables (LW, UW). 2. A write occurs during the overlap of E low and W low. 3. Both Write Enables must be equal to VIH for all address transitions. 4. All write cycle timing is referenced from the last valid address to the first transitioning address. 5. All latched inputs must meet the specified setup and hold times with stable logic levels for ALL falling edges of address latch (AL) and data latch (DL). 6. If E goes high coincident with or before W goes high the output will remain in a high impedance state. 7. If E goes low coincident with or after W goes low the output will remain in a high impedance state. 8. Transition is measured 500 mV from steady-state voltage with output load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, tWLQZ is less than tWHQX for a given device. 9. If G goes low coincident with or after W goes low the output will remain in a high impedance state.
MCM67A618A 10
MOTOROLA FAST SRAM
LATCHED WRITE CYCLES
AL (ADDRESS LATCH) tALHALL tAVALL tALLAX A (ADDRESS) A1 tAVALH tWHAX tEVALH E (CHIP ENABLE) tALHWH tALHWL LW, UW (WRITE ENABLE) tDVWH tWHDX DATA-IN D(A1) tDLHWH DL (DATA LATCH) tDVDLL tDLLDX D(A2) tWHDLH tDLHEH tDVEH D(A3) D(A4) tEHDLH tAVWL tWLWH tWHALH tWLEH A2 tEVALL tALLEH A3 tAVAV tAVEL tELEH A4 tAVEH tEHAX
tELWH tAVWH
tEHDX
tWHQX Q (DATA OUT)
tWLQZ
ORDERING INFORMATION
(Order by Full Part Number) MCM 67A618A
Motorola Memory Prefix Part Number
Full Part Numbers -- MCM67A618AFN10
X
XX
Speed (10 = 10 ns, 12 = 12 ns, 15 = 15 ns) Package (FN = PLCC) MCM67A618AFN12 MCM67A618AFN15
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM67A618A 11
PACKAGE DIMENSIONS
FN PACKAGE 52-LEAD PLCC CASE 778-02 B -NY BRK D -L52 LEADS ACTUAL
0.007 (0.180) U
M
T L -M
M
S
N
S
0.007 (0.180)
T L -M
S
N
S
-MW D V A 0.007 (0.180)
M
Z
(NOTE 1) 52
1
X VIEW D-D T L -M
S
G1 0.010 (0.250)
S
T L -M
S
N
S
N
S
Z R 0.007 (0.180)
M
T L -M
S
N
S
H
0.007 (0.180)
M
T L -M
S
N
S
C
(NOTE 1) 52
E
0.004 (0.100)
K1 K F VIEW S 0.007 (0.180)
M
G G1
J
-T-
SEATING PLANE
VIEW S 0.010 (0.250)
S
T L -M
S
N
S
T L -M
S
N
S
NOTES: 1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 52 LEADS. 2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. 7. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 8. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 -- 0.025 -- 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 -- 0.020 2 10 0.710 0.730 0.040 --
MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 -- 0.64 -- 19.05 19.20 19.05 19.20 1.07 1.21 1.07 1.21 1.07 1.42 -- 0.50 2 10 18.04 18.54 1.02 --
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MCM67A618A 12
MCM67A618A/D MOTOROLA FAST SRAM

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